Browse Prior Art Database

Attached Support Processor with Shared Cache and Execution Unit

IP.com Disclosure Number: IPCOM000078992D
Original Publication Date: 1973-Apr-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Schmookler, MS: AUTHOR

Abstract

Two or more central-processing units CPU can form a highly flexible computing system, particularly when at least one of the CPUs has the capability of-simultaneously executing two separate streams of instructions I.

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Attached Support Processor with Shared Cache and Execution Unit

Two or more central-processing units CPU can form a highly flexible computing system, particularly when at least one of the CPUs has the capability of-simultaneously executing two separate streams of instructions I.

A suitable CPU is shown in Fig. 1. For each 1-stream there is a separate control unit ICU1 and ICU2, each of which communicates with a channel interface unit CIU1 and CIU2, respectively. Each CIU may control a given number of channels. ICU1 and ICU2 may alternately share a single high-speed instruction execution unit IEU and a single address generation unit AGU. Storage references will first be directed to a high-speed buffer or cache. If the requested data is not in the cache, main storage MS will be referenced under control of the main storage control unit MSC. MS is logically partitioned into two sections, M1 and M2, which will be referenced by ICU1 and ICU2, respectively.

A highly flexible three-CPU system is shown in Fig. 2. Primary system control is with CPU1 which is a dual I-stream processor, as described above. The supervisory program is run in ICU1. It places incoming jobs on a file JOBQ. ICU1 may execute a job itself, or it may send it to ICU2 (implying some means for moving data between the partitions of memory M1 and M2), or it may send it to CPU2 or CPU3 via channel-to-channel connections CTC. An additional FILE may be shared as desired within the system. In the event that C...