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Simultaneous Diffusion and Alignment Step Formation Technique

IP.com Disclosure Number: IPCOM000079025D
Original Publication Date: 1973-Apr-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Beyer, KD: AUTHOR

Abstract

This process is applicable to diffusion of an impurity by paint-on diffusion sources.

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Simultaneous Diffusion and Alignment Step Formation Technique

This process is applicable to diffusion of an impurity by paint-on diffusion sources.

During the heat treatment of arsenic doped oxide, beta-cristobalite crystals are formed above 900 degrees C in the arsenic doped oxide. In the removal of the arsenic doped oxide, in reopening the masked windows for the reoxidation process, difficulty is encountered in removing the beta-cristobalite crystals because of their slow etch rate.

In this process, a masking layer 10 of SiO(2) is deposited on semiconductor wafer 12 in the conventional manner. Diffusion windows 14 are formed in the layer 10, as shown in Fig. 1. Subsequently, a source layer 16 is deposited on the surface of wafer 12 which source layer may contain a suitable impurity, as for example arsenic. Layer 16 can be deposited by paint-on techniques or pyrolytic deposition. Following the deposition of layer 16, the wafer is conventionally heated to drive the impurity into the semiconductor body 12.

In this process, a small amount of HCl gas is added to the diffusion ambient as indicated in Fig. 2. This HCl gas diffuses through the masking oxide and the arsenic doped oxide and reacts with the silicon surface forming volatile reaction products. The etch rate of the silicon is determined directly by the oxide thickness above the silicon surface. The silicon etch rate is, therefore, higher in the openings 14 of masking oxide 10 than in the areas that are maske...