Browse Prior Art Database

Memory Array using Storage Mode Effect Cells

IP.com Disclosure Number: IPCOM000079043D
Original Publication Date: 1973-Apr-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 41K

Publishing Venue

IBM

Related People

Robbins, GJ: AUTHOR [+2]

Abstract

The present system utilizes the storage-mode circuit described in U. S. Patent 3,696,285 for cells in a monolithic memory array.

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Memory Array using Storage Mode Effect Cells

The present system utilizes the storage-mode circuit described in U. S. Patent 3,696,285 for cells in a monolithic memory array.

With reference to the basic cell shown in Fig. 1, when the collector of the cell is made negative, current flows through the diode bypass around the emitter- base into the collector. The timing chart of Fig. 2 shows this action in the region called Q(s)(or stored charge). By waiting for a time, t(w), it is possible to recover charge Q(r) from the cell by biasing the collector positive. The graph of Fig. 3 shows, conceptually, that this recovered charge is diminished by time such that if t(w) is very long, very little charge is left. The characteristic shown in Fig. 3 is a critical design parameter of the present cells.

An array of storage-mode cells is shown in Fig. 4. Here the characters w,b denote word and bit lines in the array. The operation of the memory consists of writing data by raising the bit line with reference to the word line. A cell thus selected will be charged by current flowing up the bit line, around the emitter- base bypass diode, into the collector of cell Sw,b, and into the word line. This cell is now defined to contain a "1" bit. To read out any cell, the word line potential is made higher than the bit line, and the cell is depleted of some or all charge stored in it. The current which flows in the bit line when Sw,b has been previously written with a 1, is detected by standard bit line support circuits, not shown. A read-out operation is then followed by a write-back operation, wherein the cell read is rewritten into as described previously.

If a cell is not to be written into (e.g., is to contain a "0" bit), then the bit...