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Memory Using Dayem Bridge Interferometers

IP.com Disclosure Number: IPCOM000079065D
Original Publication Date: 1973-Apr-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Schulz Dubois, EI: AUTHOR

Abstract

This memory requires only two types of access lines and only two devices per cell. The drawing depicts a single cell. It contains two Dayem bridges, each capable of carrying a maximum Josephson current I(o) and is accessed by a word line and a bit line. The bit line couples through mutual inductance M to the cell circuit of inductance L and it serves both for writing and reading. The memory comprises a two-dimensional array of identical cells which are connected by word lines and bit lines.

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Memory Using Dayem Bridge Interferometers

This memory requires only two types of access lines and only two devices per cell. The drawing depicts a single cell. It contains two Dayem bridges, each capable of carrying a maximum Josephson current I(o) and is accessed by a word line and a bit line.

The bit line couples through mutual inductance M to the cell circuit of inductance L and it serves both for writing and reading. The memory comprises a two-dimensional array of identical cells which are connected by word lines and bit lines.

There are two ways of using the memory. In asymmetric operation, a binary 1 is stored in terms of a ring current I(R) = (1 - 2 epsilon) I(o) where epsilon represents a tolerance margin of a few percent, while a binary 0 is stored in terms of nearly vanishing ring current I(R) = epsilon I(o). Writing is achieved by simultaneous application of a word current I(W) = 2 (1 - epsilon) I(o) and a bit current I(B) = L I(o) (1 - epsilon)/M for writing 1, or zero bit current for writing 0. After termination of these write currents, the above ring currents are present. Half-selection, i.e., the temporary application of a bit currently only, does not alter the stored ring current. The read operation requires application of the above word current only. For a stored 1, a voltage pulse is induced in the bit line whose area is V dt = M 1(o) (1 - 3 epsilon), while no voltage pulse is induced for a stored
0. After the read operation all cells along a wr...