Browse Prior Art Database

Vertical One Device Memory Cell

IP.com Disclosure Number: IPCOM000079069D
Original Publication Date: 1973-May-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Smith, WM: AUTHOR

Abstract

This cell structure for a memory array provides a very high-density one-device memory cell, of the type described in U. S. Patent 3,387,286, entitled Field-Effect Transistor Memory, which is limited substantially only by the area of the capacitor of the cell. The capacitor overlies and is connected to a field-effect transistor.

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Vertical One Device Memory Cell

This cell structure for a memory array provides a very high-density one- device memory cell, of the type described in U. S. Patent 3,387,286, entitled Field-Effect Transistor Memory, which is limited substantially only by the area of the capacitor of the cell. The capacitor overlies and is connected to a field-effect transistor.

The cell may be constructed by employing the following steps:
1) Provide a substrate which may be an N-type epitaxial grown

layer.
2) Grow thin thermal oxide on the substrate.
3) Deposit thin silicon nitride or equivalent dielectric which

acts as a diffusion barrier.
4) Etch the nitride and oxide where diffusions are required

for the source and drain of the field-effect transistor, for

forming bit/sense diffusions and storage-node diffusions,

respectively.
5) Diffuse P+ material for the source and drain.
6) Etch away the silicon nitride, except over the gate area of

the field-effect transistor.
7) Grow thick thermal oxide. 8) Deposit a first polysilicon layer doped with P-type material, or a metal layer. 9) Etch the polysilicon layer to form in the memory array word lines in contact with the silicon nitride at the gate area.
10) Deposit a thick pyrolytic oxide.
11) Etch contact holes through the pyrolytic and thermal oxides

to the storage-node diffusion of the field-effect transistor.
12) Deposit a second polysilicon layer doped with P-type

material.
13) Etch the second polysilicon layer to form a storage-n...