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Storage Reconfiguration

IP.com Disclosure Number: IPCOM000079070D
Original Publication Date: 1973-May-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 5 page(s) / 71K

Publishing Venue

IBM

Related People

Fox, JL: AUTHOR [+4]

Abstract

The following describes a method whereby hardware reconfigures storage in either a unit or multiprocessing system. The uniprocessor reconfiguration technique allows the operator to take off-line any storage frame he wishes and run concurrent on-line maintenance. It is compatible with the multiprocessor storage reconfiguration, thus making the addition of the multiprocessor feature an easy task.

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Storage Reconfiguration

The following describes a method whereby hardware reconfigures storage in either a unit or multiprocessing system. The uniprocessor reconfiguration technique allows the operator to take off-line any storage frame he wishes and run concurrent on-line maintenance. It is compatible with the multiprocessor storage reconfiguration, thus making the addition of the multiprocessor feature an easy task.

A description will first be given as to how floating addressing in a multiprocessing (MP) machine will operate. A storage which is 8-way interleaved will be available in a MP system. Each CPU will have physically attached to it 4 interleaved storages. Fig. 1 depicts such a memory configuration. In Fig. 1, memory is divided horizontally across 6 megabytes of storage into 12-512K byte segments or bands. (In Fig. 1, each CPU has 3 megabytes of storage.) Therefore, each band contains 512K bytes of storage across a interleaves. Each band can now be said to represent a physical spectrum of memory. A rotary switch is provided for each band. Any particular band can be made to logically represent any one of the 12-512K byte memory segments; i.e., a core in band 0, depending on how switch 0 was set, could logically represent any one of the 12 address ranges. Two switches are also provided with each one of the 12 rotary switches. These two switches enable or disable one or both processors from going to a particular band of storage.

If the MP system is set up such that 4-way interleave or less is in operation, then the 512K byte bands are arranged differently. For all interleave modes switch 0 corresponds to band 0, switch 1 to band 1, etc. For less than 8-way interleaving, switches 0, 2, 4, 6, 8, 10 represent six bands in CPU A, while switches 1, 3, 5, 6, 9, 11 represent the six bands in CPU B.

When all the switches are properly set, the address range a particular band will cover is put into a four-bit register. Also loaded in corresponding registers is information concerning which processor or processors will be enabled or disabled from entering a particular band. If band 0 is given the address range of 0 to 512K, 0000 would be loaded into the register for switch 0. An address range of 512K to 1024K is represented by 0001, etc.

Two mechanisms make use of how the address switches and the enable/disable switches are set. These mechanisms are known as the half-float stations. The function of the half-float station is to determine the interleave a memory request will access. The basic function of the full-float station is to determine the select level of a particular memory request and to check for Invalid addressing. If the select level and the interleave of a particular request is known, then selecting the logical storage unit (L:SU) becomes an easy task. The half- float function is accomplished before the different requests enter memory priority networks. The full-float function is done while a unique request is on the way to s...