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Browse Prior Art Database

Josephson Ring Shift Register

IP.com Disclosure Number: IPCOM000079111D
Original Publication Date: 1973-May-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Hamel, HC: AUTHOR

Abstract

A shift register is provided in which each gate or stage consists of three Josephson tunnelling gates J1, J2 and J3, as shown in Fig. 1. Gate 1 of the shift register operates by resetting device J2 with phase current 01, thereby causing the input Iin to flow through device J1. The input signal at 02 time either switches device J1 causing the current Iin to remain flowing through device J1 or does not cause device J1 to switch, thereby causing the current Iin to flow through device J2. Therefore, the state of the stage is either the current Iin flowing through J1 or J2.

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Josephson Ring Shift Register

A shift register is provided in which each gate or stage consists of three Josephson tunnelling gates J1, J2 and J3, as shown in Fig. 1. Gate 1 of the shift register operates by resetting device J2 with phase current 01, thereby causing the input Iin to flow through device J1. The input signal at 02 time either switches device J1 causing the current Iin to remain flowing through device J1 or does not cause device J1 to switch, thereby causing the current Iin to flow through device J2. Therefore, the state of the stage is either the current Iin flowing through J1 or J2.

At clock time 03 the state of the stage is passed on to the next gate. That is, if a signal appeared at the control line of device J1 at 02 time), device J3 will switch and present a current to the control of device J1' at clock time 03. Thus, the state of the stage is passed on to the next stage via the condition of J3 at the proper phase time. The subsequent stages of the shift register operate in exactly the same manner except for the necessary changes in timing, as shown in Fig. 2 for gates 2, 3 and 4.

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