Browse Prior Art Database

FET Digital Photodetector Processor

IP.com Disclosure Number: IPCOM000079123D
Original Publication Date: 1973-May-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 102K

Publishing Venue

IBM

Related People

Bowen, AJ: AUTHOR [+5]

Abstract

This field-effect transistor (FET) digital photodetector processor converts the electrical current signal passing through the photosensitive device of an optical sensor into a logical voltage signal, indicating whether the optical sensor sensed the presence or absence of data indicia.

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FET Digital Photodetector Processor

This field-effect transistor (FET) digital photodetector processor converts the electrical current signal passing through the photosensitive device of an optical sensor into a logical voltage signal, indicating whether the optical sensor sensed the presence or absence of data indicia.

The optical sensor 10 in Fig. 1 includes a light source 11 and a photosensitive device 12. Sensor 10 is of the type incorporated into machines for reading punched-record cards. The output of 12 is a current signal which is proportional to the intensity of incidental light. This current signal, as shown in Fig. 5, varies in amplitude according to the presence or absence of a hole in a card and is applied to contrast control and square-root function circuit 15, Fig. 1. This circuit as shown in Fig. 2 includes FET transistors 16, 17 and 18.

The input from photosensitive device 12 is applied to FET 18 and a threshold level sample signal is applied to FET 16. Circuit 15 takes advantage of the FET current and voltage transfer characteristics, whereby Vin is proportional to the square root of Iin. This results in signal compression and provides a wider dynamic range. The output from circuit 15 is a voltage level Vin which is applied to block 25, which includes comparators 26, 27, 28 and 29 as shown in detail in Fig. 4. Comparators 26-29 each have one input commonly connected to the Vin output of circuit 15. Circuit 15 in Fig. 4 is schematically illustrated as a resistor R6. The other inputs to comparators 26-29 come from the reference voltage level block 40 of Fig. 1, which is represented as a voltage divider network consisting of resistors R1-R5, as shown in Fig. 4. The resistors R1-R5 are implemented with FET devices. The FET digital photodetector in Fig. 4 is a simplified showing to illustrate the basic system elements and functions.

Comparators 26-29 each consist of a circuit as shown in Fig. 3, and include FET devices connected to be responsive to small changes in Vin applied to terminal 34 and provide a high-voltage gain at terminal 35. The associated reference voltage level is applied to terminal 36. The FET's 1, 2, 3, 4 and 5 form a first stage and the in and out-of-phase voltages therefrom are shifted down in magnitude, by two resistor dividers formed by FET's 6, 7 and 8, 9, respectively. The lower magnitude signals are then amplified by the second stage formed by FET's 19, 20, 21, 22 and 23.

The outputs of the comparators of block 25 are fed into video processor 50, which performs a smoothing function with respect to the data bits developed by comparators 26-29. Video processor 50 essentially includes elements such as inverters 51-54, Fig. 4, for performing the smoothing function, i.e., to account for the characteristics of the FET circuitry. The resulting digital code which has been smoothed by video processor 50 is stored in polarity-hold latches 61-64, Fig. 4, in response to a threshold level sample signal. T...