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Modular Solid State Power Sequencing

IP.com Disclosure Number: IPCOM000079124D
Original Publication Date: 1973-May-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 75K

Publishing Venue

IBM

Related People

Goodew, CD: AUTHOR [+3]

Abstract

This power sequencing system includes sequencing modules connected together for controlling power-up and power-down of electrical power supplies. Each module controls an associated power supply and interacts with other modules whereby if a fault occurs in the associated power supply during a power-up sequence, no supplies of lower sequencing priority are energized and the faulty supply powers-down. After a predetermined time delay, the higher priority supplies are powered-down in sequence. If a fault occurs after all power supplies have been powered-up, the power supplies power-down in sequence from low to high priority. Fault conditions are stored and displayed to indicate which power supply failed and the cause of the failure conditions, such as overvoltage, overcurrent and undervoltage.

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Modular Solid State Power Sequencing

This power sequencing system includes sequencing modules connected together for controlling power-up and power-down of electrical power supplies. Each module controls an associated power supply and interacts with other modules whereby if a fault occurs in the associated power supply during a power-up sequence, no supplies of lower sequencing priority are energized and the faulty supply powers-down. After a predetermined time delay, the higher priority supplies are powered-down in sequence. If a fault occurs after all power supplies have been powered-up, the power supplies power-down in sequence from low to high priority. Fault conditions are stored and displayed to indicate which power supply failed and the cause of the failure conditions, such as overvoltage, overcurrent and undervoltage.

In Fig. 1, power sequencing modules 10, 20 and 30 are connected to control power supplies 15, 25 and 35, respectively, where module 10 is the high-priority module. Power-up sequencing is initiated by closing momentary switch 45 after a system reset signal has been applied to reset terminal 40. This causes latch 46 to be set. The set output of latch 46 is applied to module 10 and to time delay 47.

The output of time delay 47 is applied to each module and to a reset input of latch 48. Modules 10, 20 and 30 are interconnected in a manner that module 10 must power-up before module 20 can power-up. Module 10 provides a conditioning signal on conductor 50 which is applied to input terminal 49 of module 20. Similarly, module 20 provides a conditioning signal on conductor 50 to input terminal 49 of module 30.

Each module, such as module 20 in Fig. 2, includes an AND circuit 51, which passes a Start control signal on conductor 70 to the associated power supply when all input conditions are satisfied. AND circuit 51 has an input from terminal 49, which is connected to the output conductor 50 from the adjacent higher priority module 10. The signal on conductor 50 is at an up level if none of the inputs to NOR circuit 57 are at an up level. This condition is assured at power-up time by the signal from time delay 47, which inhibits via conductor 71 generation of signals indicating undervoltage, no voltage, and an on-off-down sequence out. Input terminal 75 is connected to output conductor 76 of the adjacent lower priority module 30. The signal on conductor 76 is at an up level because of the signal from time delay 47. This signal is passed by inverter 60 to hold latch 62 reset. This causes inverter 63 to have an up level at its output. The other inputs to AND 51 are from NAND 53 and NOR 61. The signal from NAND 53 is at an up level at this time, because of the signal from time delay 47. The signal from NOR 61 is also at an up level, because overvoltage latch 68 and overcurrent latch 66 are reset. In Fig. 3, it is seen th...