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Full Capacity Small Size Microprogrammed Control Unit

IP.com Disclosure Number: IPCOM000079125D
Original Publication Date: 1973-May-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Frye, HE: AUTHOR [+2]

Abstract

This control unit comprises an instruction storage for storing microinstructions without repetitions and an address storage for storing addresses of microinstructions which make up a microprogram. Through the use of a mask, which is stored along with the address in the address storage, each word in the instruction storage is capable of supplying a plurality of microinstructions to the system. The masking technique involved enables construction of control units of reduced physical size, without reduction of the number of microinstructions contained therein.

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Full Capacity Small Size Microprogrammed Control Unit

This control unit comprises an instruction storage for storing microinstructions without repetitions and an address storage for storing addresses of microinstructions which make up a microprogram. Through the use of a mask, which is stored along with the address in the address storage, each word in the instruction storage is capable of supplying a plurality of microinstructions to the system. The masking technique involved enables construction of control units of reduced physical size, without reduction of the number of microinstructions contained therein.

Instruction storage 20 contains microwords each of which is divided into a number of fields, indicated symbolically by broken vertical lines, each field containing a microorder. Words in storage 20 are accessed from instruction storage address register (ISAR) 22. Microwords are read from storage 20 to gates 24-29, the outputs of which provide micro-orders to instruction storage data register (ISDR) 30 which holds a microinstruction. Connected to ISDR 30 is a late read-only storage data register 32, in which certain microorders are saved when a new microinstruction is read into ISDR. Decoders 34-40 are provided to decode the microorders.

Each word within address storage 42 contains the address of a word in storage 20, a mask and also a control field. When words in storage 42 accessed from an address-storage address register (ASAR) 44 are read, the control and...