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Adaptable Register Element

IP.com Disclosure Number: IPCOM000079126D
Original Publication Date: 1973-May-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 23K

Publishing Venue

IBM

Related People

Maholick, AW: AUTHOR

Abstract

The diagram shows a logical element which can serve as either a shift register element (D Flip-Flop) or as a memory element (T Flip-Flop), depending on the condition of one of its inputs. A gated J-K flip-flop 1 of the type shown in the July 1971 IBM Technical Disclosure Bulletin Vol. 14 No. 2, pages 491 and 492, is provided to generate complementary output signals on lines 2 and 3. A J-K flip-flop has the characteristic that when a clock signal is supplied on a line 8, its outputs shift, if necessary, to correspond to the one of the two inputs which is at an up level but if both inputs are up, the output levels will be reversed. There will be no change if both inputs are at a down level.

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Adaptable Register Element

The diagram shows a logical element which can serve as either a shift register element (D Flip-Flop) or as a memory element (T Flip-Flop), depending on the condition of one of its inputs. A gated J-K flip-flop 1 of the type shown in the July 1971 IBM Technical Disclosure Bulletin Vol. 14 No. 2, pages 491 and 492, is provided to generate complementary output signals on lines 2 and 3. A J- K flip-flop has the characteristic that when a clock signal is supplied on a line 8, its outputs shift, if necessary, to correspond to the one of the two inputs which is at an up level but if both inputs are up, the output levels will be reversed. There will be no change if both inputs are at a down level.

One input of the J-K flip-flop 1 is connected to a T input signal line 4 and the other input of flip-flop 1 is connected to the output 5 of an exclusive OR circuit 6. The inputs of exclusive OR 6 are the T input line 4 and a D input line 7. The circuit operates so that if the D line 7 is at a down level when the clock signal line 8 comes up, the flip-flop 1 will reverse its outputs 2 and 3 to the opposite state, thus operating as a conventional binary trigger. If, however, the D line 7 is at an up level, then at the clock pulse on line 8, the output lines will, if necessary, shift so that output line 2 will correspond to the state of the T line 4 and output line 3 will assume the complementary state. In this condition, the logic will be operating as a...