Browse Prior Art Database

Multiple Channel Bus

IP.com Disclosure Number: IPCOM000079129D
Original Publication Date: 1973-May-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Related People

Capowski, RS: AUTHOR [+2]

Abstract

Two logically and physically independent buses for information and controls, allows data to be transferred simultaneously along different data paths from input/output to memory.

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Multiple Channel Bus

Two logically and physically independent buses for information and controls, allows data to be transferred simultaneously along different data paths from input/output to memory.

The channels attached to the system are divided into two groups. The first group comprises channels 1, 2 and 3 and the second group comprises channels 4, 5 and 6. Channels 4, 5 and 6 are attached to bus A Which transfers data from one of the channels to a register A. The register A feeds an OR circuit 10 which is connected to the input to buffers 12. The buffer 12 is divided into six areas, one area for each of the channels.

The second group of channels, 1, 2 and 3, feed a register B which is also connected to OR circuit 10. Priority circuit A receives requests 1REQ, 2REQ and 3REQ from each of the channels 1, 2 and 3, and busy signals 1BUSY, 2BUSY and 3BUSY from each of the buffers 1, 2 and 3. The highest priority channel is channel 1 and the lowest priority channel is channel 3. The priority responses 1RESP, 2RESP and 3RESP are generated in accordance with this priority ranking.

In a similar manner, a priority circuit B is provided to receive requests from channels 4, 5 and 6 and to combine with busy responses from buffers 4, 5 and 6, to provide a response 4, 5 or 6 to the channels. Channel 4 has the highest priority while channel 6 has the lowest priority. The priority circuits A and B are logically independent and, therefore, priority can be granted to the highest priority channel in either or both groups, without interference from one another.

For example, assume that channels 1, 3 and 6 request data transfer. Assume, also that buffer 1 is busy. The 1 request line will be en...