Browse Prior Art Database

One Device Cell Layout

IP.com Disclosure Number: IPCOM000079147D
Original Publication Date: 1973-May-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Kruggel, RH: AUTHOR

Abstract

The layout for the one-device cell has a Z-axis symmetry to minimize changes in thin-oxide capacitance due to mask shifts, resulting in minimum cell size.

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One Device Cell Layout

The layout for the one-device cell has a Z-axis symmetry to minimize changes in thin-oxide capacitance due to mask shifts, resulting in minimum cell size.

In the one-device memory cell, such as that illustrated in Fig. 1 showing two cells, and described in detail in U. S. Patent 3,387,286, granted to R. H. Dennard, the stray capacitance to a line is a dominant factor in the circuit performance or semiconductor chip size. Typically. this stray capacitance comprises the junction capacitance in diffused lines and the gate-to-drain, or gate-to-source capacitance, due to the thin oxide required under the gate electrode of a field-effect transistor (FET) coupled to the line. When a layer of thin oxide, such as silicon dioxide, is required at or adjacent to, e.g., a diffused line, shifts in the mask used to locate the thin-oxide layer with respect to the diffusion in the semiconductor, cause substantial variations in stray capacitance to the line.

By utilizing a Z-axis symmetry layout, as indicated in Fig. 2, the sum of the gate-to-drain capacitance Cdg1 formed in FET 1 and the gate-to-drain capacitance Cdg2 formed in FET 2, i.e., the thin-oxide capacitance to the diffused bit sense (B/S) line caused by FET 1 and FET 2, is independent of mask shifts. The point of symmetry is indicated by point 10. Capacitance Cdg1 is formed by the thin oxide of FET 1 between the diffused B/S line and metal word line 1, or the gate electrode of FET 1, and capacitance Cdg2 is similarly formed by FET 2 between the diffused B/S line and metal word line 2. Any mask shift whi...