Browse Prior Art Database

Semiconductor Chip Pad Protect Device

IP.com Disclosure Number: IPCOM000079148D
Original Publication Date: 1973-May-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Kalter, HL: AUTHOR

Abstract

Static voltage discharge from a chip pad through a gated vertical NPN transistor prevents oxide breakdown on the chip, particularly the gate oxide of field-effect transistors connected to the pad.

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Semiconductor Chip Pad Protect Device

Static voltage discharge from a chip pad through a gated vertical NPN transistor prevents oxide breakdown on the chip, particularly the gate oxide of field-effect transistors connected to the pad.

A schematic diagram of the gated vertical NPN transistor is illustrated in Fig.
1. The transistor 10 has a base 12, an emitter 14 connected to pad 16 and a collector 18 connected to substrate 20 of the chip. The junction 22 formed between base 12 and collector 18 is gated to produce premature breakdown at junction 22. The gating element for junction 22 is indicated at 24.

A cross-sectional view of the chip illustrating the gated vertical NPN transistor of Fig. 1 is shown in Fig. 2, with corresponding elements identified by like reference numerals. The gating element 24 includes a thin layer 26 of silicon dioxide overlying the base-collector junction 22 at the surface of substrate 20. A layer of conductive polysilicon 28 disposed over thin-oxide layer 26 is ohmically connected to the substrate 20, which is an N substrate, through aluminum contacts 30 and 32 and N/+/ region 34. By biasing the polysilicon layer 28 to the voltage of the N/-/ substrate 20, a field is produced at the base-collector junction 22 near the surface of the substrate 20, which modifies the depletion region in this area of junction 22 to cause premature breakdown of junction 22.

The I-V characteristic across the gated vertical NPN transistor is illustrated in Fig...