Browse Prior Art Database

Bipolar and FET Integration on a Common Chip

IP.com Disclosure Number: IPCOM000079149D
Original Publication Date: 1973-May-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Kalter, HL: AUTHOR

Abstract

The circuit provides integration of relatively fast low-power bipolar logic circuits and high-density low-power field-effect transistor (FET) memories on a common semiconductor chip.

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Bipolar and FET Integration on a Common Chip

The circuit provides integration of relatively fast low-power bipolar logic circuits and high-density low-power field-effect transistor (FET) memories on a common semiconductor chip.

The circuit in Fig. 1 shows a bipolar logic family 10 and a P-channel FET circuit 12 interconnected through a converter 14. The logic family 10 includes a first current switch having a PNP transistor 16 connected at its emitter to a constant-current source 18, and at its collector to a logic input A and to the base of an NPN transistor 20. Transistor 20 has its emitter connected to the substrate of the chip and its collector to a +1.7 volt source of potential through resistor 22. The base of transistor 16 is connected to the emitter of transistor 20. A second current switch, similar to the first current switch, has a logic input B and is coupled to the collector of transistor 20. These two current switches form a NOR gate.

The converter 14 includes a PNP transistor 24 having its emitter connected to the collector of transistor 20, its base connected to the substrate and its collector connected to the base of NPN transistor 26. The collector of transistor 26 is connected to the substrate, and its emitter is coupled through resistor 28 to a -10 volt source of potential.

The FET circuit 12 comprises an FET 30 having a gate coupled to the emitter of NPN transistor 26, a drain connected to ground, and a source connected to an output terminal an...