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Page Invalidation Technique for Multiprocessing Systems

IP.com Disclosure Number: IPCOM000079155D
Original Publication Date: 1973-May-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Brinck, GM: AUTHOR

Abstract

The architecture of IBM System/370 Relocate (DAT (Dynamic Address Translation) Feature) Multiprocessor, requires that the invalidation of a translation table entry that is shared by multiple CPUs be synchronized n all of those CPUs. To do this, a computer program is provided c consisting of two distinct functions known as "MASTER" and "SLAVE". The MASTER and SLAVE functions both reside in storage addressable by all CPUs in the configuration. The MASTER function requires the use of a facility which can signal another CPU from the one on which MASTER is executing, and cause that other CPU to invoke the SLAVE function. In OS/VS2-Rel. 2, this facility is provided by the Inter-processor Communication (IPC) function. Neither MASTER nor SLAVE can reside in the virtual storage to be invalidated.

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Page Invalidation Technique for Multiprocessing Systems

The architecture of IBM System/370 Relocate (DAT (Dynamic Address Translation) Feature) Multiprocessor, requires that the invalidation of a translation table entry that is shared by multiple CPUs be synchronized n all of those CPUs. To do this, a computer program is provided c consisting of two distinct functions known as "MASTER" and "SLAVE". The MASTER and SLAVE functions both reside in storage addressable by all CPUs in the configuration. The MASTER function requires the use of a facility which can signal another CPU from the one on which MASTER is executing, and cause that other CPU to invoke the SLAVE function. In OS/VS2-Rel. 2, this facility is provided by the Inter-processor Communication (IPC) function. Neither MASTER nor SLAVE can reside in the virtual storage to be invalidated.

When the function executing on a given CPU determines that a translation table entry must be invalidated, it calls the MASTER function and indicates the entry to be changed. MASTER sets an indicator to a predefined value, and then uses the IPC facility to invoke the SLAVE function on the other CPUs which have access to the entry. When all the desired CPUs are executing the SLAVE function (described below), the MASTER function is assured that no other CPU is accessing the table entry, as is required by the hardware architecture. It switches the table entry to invalid and resets the indicator value. Meanwhile, the SLAVE routin...