Browse Prior Art Database

Enhancement Mode Operation of Depletion Mode FET Devices

IP.com Disclosure Number: IPCOM000079165D
Original Publication Date: 1973-May-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Pricer, WD: AUTHOR

Abstract

All field-effect transistor (FET) processes cannot result in enhancement-mode devices. For example, junction FET's, N channel metal-oxide semiconductor (MOS), Schottky junction FET devices are depletion-mode devices. Some may be made enhancement mode by use of a substrate bias when they are used for digital circuits.

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Enhancement Mode Operation of Depletion Mode FET Devices

All field-effect transistor (FET) processes cannot result in enhancement- mode devices. For example, junction FET's, N channel metal-oxide semiconductor (MOS), Schottky junction FET devices are depletion-mode devices. Some may be made enhancement mode by use of a substrate bias when they are used for digital circuits.

When the use of such a substrate bias is inconvenient or not permitted or when lower power requirements dominate, such depletion-mode devices can still be used if the following circuit family is used. Shown here is a NOR gate which uses depletion mode devices, without requiring the biasing of the substrate in which they are created. The NOR gate consists of transistors 10 and 12 in series with each other and with a trio of input FET's 14, 16, and 18.

The drain 20 of transistor 10 is coupled to a positive power supply +V and its gate 22 is driven by an input pulse B1. The source 24 of transistor 10 is in turn coupled to the drain 26 of transistor 12, whose gate 2A is driven by B2 and whose source 30 is coupled to a common point 32, to which is also connected the drains 34, 36, and 38 of the three input transistors 14, 16, and 18. The gates 40, 42, and 44 of these input transistors are coupled to input signals sources A, B, and C. The sources of the input FET's 14, 16, and 18 are coupled to ground.

A line 46 is coupled to the source-drain interconnection between FET's 10 and 12, and through a ca...