Browse Prior Art Database

Repeated Use of a Program Part

IP.com Disclosure Number: IPCOM000079176D
Original Publication Date: 1973-May-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 66K

Publishing Venue

IBM

Related People

Gigling, V: AUTHOR [+6]

Abstract

The method described permits program segments being repeatedly used, without the segments concerned having to be stored several times at different storage locations within the processing unit, or without the segments having to be detached from the program and having to be stored separately as a subroutine. The method utilizes several instruction address registers and is particularly suitable for processing units, in which the program instructions are selectively addressed by one of several address registers.

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Repeated Use of a Program Part

The method described permits program segments being repeatedly used, without the segments concerned having to be stored several times at different storage locations within the processing unit, or without the segments having to be detached from the program and having to be stored separately as a subroutine. The method utilizes several instruction address registers and is particularly suitable for processing units, in which the program instructions are selectively addressed by one of several address registers.

Each instruction address register is connected either to its own or to a common address incrementing unit, which after each instruction addressing operation increments the address value by a constant value, thus setting the register to the address of the next program instruction. Deviating from this, the instruction address registers can also take the form of instruction counters, which every time an instruction is fetched from storage are advanced to the address of the successor instruction.

The figure shows a program P, the initial instruction INSTR 1 of which is stored at address A1 and which consists of a plurality of instructions. Within this program, instructions INSTR 10 to INSTR 20 represent a program segment which is to be called several times in the course of program P. The structure of this program segment which may comprise branches or loops can be chosen at random. In the example shown, the program segment is a linear instruction sequence.

The processing unit used to execute program P is provided with four instruction address registers IAR 1 to IAR 4. Before the program is executed, initial address A1 of program P is stored in register IAR 1, whereas initial address A10 of the program segment to be executed repeatedly is stored in parallel instruction address registers IAR 2, IAR 3 and IAR 4. Under the control of register IAR 1, instructions INSTR 1 to INSTR 20 are addressed for execution, with the call of instructions INSTR 10 to INSTR 20 representing the first run of the program segment to be used repeatedly. The instruction from storage address A21, which follows instruction INSTR 20, is a branch instruction "...