Browse Prior Art Database

System Input/Output Attachment Architecture for LSI Microprocessor

IP.com Disclosure Number: IPCOM000079197D
Original Publication Date: 1973-May-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Dumstorff, EF: AUTHOR [+4]

Abstract

A data-processing system 13 includes a microprocessor (MPU) 15, having a read-only storage unit (ROS) 10, instruction decode module 12, arithmetic logic unit (ALU) 16, and a memory address module 11; data buffer 40, buffer control (BC) 41, and a large number of registers 14. External to the MPU 15 and physically housed in one of the input/output units 30 is I/O interface logic 20. Access modules (AM's) 21, 22 are designed to appear to the MPU 15 as if they were additional registers 14.

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System Input/Output Attachment Architecture for LSI Microprocessor

A data-processing system 13 includes a microprocessor (MPU) 15, having a read-only storage unit (ROS) 10, instruction decode module 12, arithmetic logic unit (ALU) 16, and a memory address module 11; data buffer 40, buffer control (BC) 41, and a large number of registers 14. External to the MPU 15 and physically housed in one of the input/output units 30 is I/O interface logic 20.

Access modules (AM's) 21, 22 are designed to appear to the MPU 15 as if they were additional registers 14.

Access module 21 reacting like a register 14 receives parameter information, such as length of data to be read or written and other information required to complete the transaction. In the same fashion, access module 22 receives the operation command, such as read or write. AM 22 also stores I/O unit 30 status data such as "busy" or "ready". Buffer data handler unit 23 controls data flow between I/O units 30 and MPU buffer 40.

To transfer from the buffer 40 to an I/O unit 30 such as a disk, the status of the particular I/O unit 30 is determined by addressing AM 22 and transferring the status information to ALU 16. ALU 16 operates status information in a fashion to generate the address in ROS 10, which contains the branch instruction in the event that the selected I/O unit is busy. If the I/O unit 30 is ready to accept data, the status information processed by ALU 16 will cause address unit 11 to select the address i...