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Intermittent Error Isolation in a Double Error Environment

IP.com Disclosure Number: IPCOM000079201D
Original Publication Date: 1973-May-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Bossen, DC: AUTHOR [+3]

Abstract

When a multiple-bit failure occurs in storage, a diagnostic program must be able to identify the failing bit locations contributing to the multiple-bit error. If one of the failures is intermittent, there is little chance that the diagnostic program will be able to identify both failing bits.

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Intermittent Error Isolation in a Double Error Environment

When a multiple-bit failure occurs in storage, a diagnostic program must be able to identify the failing bit locations contributing to the multiple-bit error. If one of the failures is intermittent, there is little chance that the diagnostic program will be able to identify both failing bits.

This arrangement allows the diagnostic to identify the intermittent bit location. When the multiple-bit error occurs, the failing address, uncorrectable error syndrome and storage configuration are logged out. If this data is manually inputted into a diagnostic program, the location of the intermittent failure can be determined by Exclusive-ORing the uncorrectable error syndrome (manual input) with the correctable error syndrome found by the diagnostic program. Both syndromes must come from the same addresses. This operation generates a correctable error syndrome which identifies the location of the intermittent bit failure.

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