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Personalization of Read Only Storage Schottky Barrier Diode Memory Array by Metallic Plugs

IP.com Disclosure Number: IPCOM000079224D
Original Publication Date: 1973-May-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Freed, LE: AUTHOR [+2]

Abstract

In read-only Schottky barrier diode memories, personalization is conventionally achieved by opening Schottky barrier contact holes through the insulative layer on a semiconductor surface, only in the array areas to which Schottky barrier contacts are to be made. The appropriate metallization is then deposited in these holes to provide the personalized Schottky barrier arrangement.

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Personalization of Read Only Storage Schottky Barrier Diode Memory Array by Metallic Plugs

In read-only Schottky barrier diode memories, personalization is conventionally achieved by opening Schottky barrier contact holes through the insulative layer on a semiconductor surface, only in the array areas to which Schottky barrier contacts are to be made. The appropriate metallization is then deposited in these holes to provide the personalized Schottky barrier arrangement.

The present approach relates to a new technique for personalization of such arrays, wherein Schottky barrier contacts are deposited at all possible contact points in the array. Then, personalization is achieved by selectively connecting a selected number of these Schottky barrier contacts into the circuit configuration. With reference to Fig. 1, assume that point 10 is a position in the array to which a Schottky barrier contact may selectively be made. Whether a "1" or a "0" is stored at position 10 in the read-only storage array, will be determined by whether a Schottky barrier contact is included in the circuit at this point. In the structure, thermal silicon dioxide layer 11 is formed on substrate 12. A layer of metal 13 about 8,000 Angstroms in thickness frames the point 10, at which the Schottky barrier contact may selectively be made. A layer of planarized silicon dioxide 14 covers the structure.

At all its potential locations at which Schottky barrier contacts may selectively be interconnected into the circuit, an opening 15 is etched through layer 14, as shown in Fig. 2. Then, as shown in Fig. 3, thermal silicon dioxide layer 11 is etched through under openings 15, to form openings 16 exposing positions 10 at all potential Schottky barrier cont...