Browse Prior Art Database

Supply Voltage Gate

IP.com Disclosure Number: IPCOM000079245D
Original Publication Date: 1973-Jun-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Lee, JM: AUTHOR [+2]

Abstract

This circuit eliminates excessive supply current encountered when the substrate of N-channel field-effect transistor (FET) chips is allowed to float.

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Supply Voltage Gate

This circuit eliminates excessive supply current encountered when the substrate of N-channel field-effect transistor (FET) chips is allowed to float.

When the substrate of N-channel FET chips is allowed to float, it attains some positive voltage equal to PN junction diode voltage above ground. This positive voltage is brought about by the reverse junction leakage current of the supply diffusions and the forward biased diode voltage of the ground diffusions, as shown in Figs. 1A and 1B. Under this forward biased substrate condition, inversion will exist around all grounded diffusions, providing a conductivity path for current to flow from the supply diffusions to the ground diffusions. The amount of current is directly proportional to the equivalent width-over-length ratio of the inverted path. In memory chips, this current can become intolerable for thermal considerations.

The circuit shown in Fig. 2 will limit this stray inversion current, while allowing normal chip operation under proper voltage conditions.

When the source-to-substrate voltage of an N-channel device is positive, the threshold voltage is always negative. Under this condition, device A of Fig. 2 will be on. By designing the on-impedance of device A to be very low compared with RA, node A will be very close to ground. The amount of current which can flow from VL will, therefore, be limited by the thin oxide device B whose gate-to- source voltage is almost zero and whose VT is n...