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Dielectric Isolation Structure for Integrated Circuit Device

IP.com Disclosure Number: IPCOM000079252D
Original Publication Date: 1973-Jun-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Chappelow, RE: AUTHOR [+4]

Abstract

In this method, devices are fabricated in dielectrically isolated monocrystalline semiconductor regions.

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Dielectric Isolation Structure for Integrated Circuit Device

In this method, devices are fabricated in dielectrically isolated monocrystalline semiconductor regions.

In the process, an N type, or P type, epitaxial layer 10 is grown on an N+ or P+ monocrystalline silicon substrate 12 by conventional techniques. As shown in Fig. 1, an oxynitride layer 14 is then deposited on layer 10 by chemical vapor deposition techniques. As shown in Fig. 2, a thick polysilicon layer 16 having a thickness sufficient to form a mechanical support is deposited on layer 14, and a nitride film 18 deposited thereon.

As indicated in Fig. 3, the substrate 12 is removed by anodic etching or a combination of mechanical or chemical mechanical polishing techniques. As indicated in Fig. 4, a thin nitride layer 20 is deposited on the single crystal silicon film 10, portions of film 20 removed to form a grid configuration defining desired dielectric isolation regions, and portions of silicon layer 10 removed by etching.

As indicated in Fig. 5, the exposed portions of layer 10 are oxidized until the silicon oxide touches the oxynitride layer 14, and layer 20 removed. Additional silicon oxide is grown or deposited forming layer 22, which together with layer 14 isolates the regions in monocrystalline silicon layer 10. Diffusions 24 and metallurgy 26 are fabricated by conventional techniques to produce devices in the resultant regions in layer 10.

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