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Checking of Control Logic

IP.com Disclosure Number: IPCOM000079272D
Original Publication Date: 1973-Jun-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Carnevale, RJ: AUTHOR

Abstract

In an LSI (large-scale integration) environment, it is becoming more imperative that self-checking hardware be integrated into the systems designs. The ability to detect a given error when the error occurs is desirable, and recreating the error with some kind of diagnostic is unacceptable. Described is a scheme to satisfy the checking of control logic within a system.

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Checking of Control Logic

In an LSI (large-scale integration) environment, it is becoming more imperative that self-checking hardware be integrated into the systems designs. The ability to detect a given error when the error occurs is desirable, and recreating the error with some kind of diagnostic is unacceptable. Described is a scheme to satisfy the checking of control logic within a system.

In a microprogrammed machine, perhaps a dozen or more control word types are defined to execute various functions within a processor. During the execution of a given control word, a fixed number of events take place in order to execute the function of the control word. Each control word, therefore, will require some fixed number of events as described by the control word type, in order to successfully execute its function. The checking mechanism is then merely an events register 1 in the figure. At the beginning of each control word execution, the appropriate event bits are turned on by event bit generator 2 dependent on the control word type. As each gated event occurs during the execution, the proper event bits are reset by events generator 3. Thus the register should be equal to zero at the end of the successful execution of each control word. If the register is not zero, an error has occurred and a control events error signal is generated by circuit 4. The bit or bits that remain on are then the event or events in error.

This scheme and others like it are the requiremen...