Browse Prior Art Database

Two Junction Josephson Memory

IP.com Disclosure Number: IPCOM000079337D
Original Publication Date: 1973-Jun-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Wolf, P: AUTHOR

Abstract

The memory array of Fig. 1 is composed of Josephson junction memory cells 1 connected to X and Y lines for addressing, and to bias lines B and read lines R. Each memory cell 1 (Fig. 2) consists of a superconducting loop 2 with a Josephson junction 3 located in one of its branches. Junction 3 is coupled to the X and Y address lines to allow for half-select operation.

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Two Junction Josephson Memory

The memory array of Fig. 1 is composed of Josephson junction memory cells 1 connected to X and Y lines for addressing, and to bias lines B and read lines R. Each memory cell 1 (Fig. 2) consists of a superconducting loop 2 with a Josephson junction 3 located in one of its branches. Junction 3 is coupled to the X and Y address lines to allow for half-select operation.

A "1" is, e.g., stored is a ring current in loop 2, a "0" as no ring current. Writing a 0 is by application of the X and Y half-select currents. If a 1 is already stored in the cell, the ring current representing it is destroyed. If a 0 was previously stored, nothing will happen. Writing a 1 is by first applying a bias current to line B and later applying the X and Y currents, which cause the junction to switch. After removing the X and Y currents, the bias current is also removed and a ring current representing a 1 is flowing continuously in loop 2.

For reading, bias current is applied first, then a read current is passed over read line R which contains a read junction. With a 0 stored, one half of the bias current will pass over read junction 4 which switches, causing a voltage drop in read line R. With a 1 stored, the resulting control current at read junction 4 will be zero and, thus, read line R remains unaffected.

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