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Multi Input Voltage/Light Sensitive Structure

IP.com Disclosure Number: IPCOM000079375D
Original Publication Date: 1973-Jun-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Bertin, CL: AUTHOR

Abstract

A light/voltage sensitive field-effect transistor (FET) structure is shown in the figure. The device can be a P (or N) channel FET, where the source is returned to ground and the drain is returned through a resistor to a power supply. The channel region is modulated by the presence of an electric field under the aluminum gates and by light in the clear regions. The electrical and light-sensitive channel regions are in series, which means the structure is digital in nature, as compared with the transparent gate analog approach. This feature permits a multi-input approach, such as the five input NAND gates shown in the figure. In addition, the thick aluminum used in the gate region is compatible with integrated circuit fabrication techniques.

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Multi Input Voltage/Light Sensitive Structure

A light/voltage sensitive field-effect transistor (FET) structure is shown in the figure. The device can be a P (or N) channel FET, where the source is returned to ground and the drain is returned through a resistor to a power supply. The channel region is modulated by the presence of an electric field under the aluminum gates and by light in the clear regions. The electrical and light- sensitive channel regions are in series, which means the structure is digital in nature, as compared with the transparent gate analog approach. This feature permits a multi-input approach, such as the five input NAND gates shown in the figure. In addition, the thick aluminum used in the gate region is compatible with integrated circuit fabrication techniques.

Regions 1, 3 and 5 are the voltage activated gates, while 2 and 4 are light sensitive. The channel region 6 is complete when all five regions have been activated, and is normally off. The region under the gates inverts due to the presence of an electric field, while in the clear region, excess carriers are generated. The channel is completed between source 7 and drain 8, drain current flows, and the drain voltage changes due to the resistor in series with the drain, not shown.

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