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Integrated Delay Circuit/Noise Rejection Circuit

IP.com Disclosure Number: IPCOM000079394D
Original Publication Date: 1973-Jun-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Chang, HC: AUTHOR [+2]

Abstract

The figure illustrates a delay circuit which will reject DC voltage level noise within predefined limits, and will also reject AC pulse noise of fairly long duration (20 microseconds or more). The circuit requires smaller silicon areas in the field-effect transistor (FET) technology than conventional circuits and gives relatively sharp rise and fall times.

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Integrated Delay Circuit/Noise Rejection Circuit

The figure illustrates a delay circuit which will reject DC voltage level noise within predefined limits, and will also reject AC pulse noise of fairly long duration (20 microseconds or more). The circuit requires smaller silicon areas in the field- effect transistor (FET) technology than conventional circuits and gives relatively sharp rise and fall times.

In the figure, devices 3, 4, 5, and 6 form a Schmitt trigger of a typical conventional design. The physical sizes of these devices in FET technology are chosen to bias node Z to a nominal 2.5 volts whenever device 4 is off, and to a level of about 0.4 volt whenever device 4 is on. The node Z voltage determines the trigger points for the Schmitt trigger. Devices 1 and 2 are operated in the saturated condition and form unidirectional charging and discharging paths for capacitor C(x). Relatively small width-to-length ratios are desired for devices 1 and 2 and are needed to extend transition times at node X required for the voltage to rise or fall.

An external series resistance separated from the main diagram by a short dashed line, may be an option to help provide long-transition times at node X. The width-to-length ratios for the device are as follows. For device 1, W-to-L equals 0.01; for device 2, 0.5; device 3, 0.05; device 4, 10.0; device 5, 1; device 6, 20.0; and a capacitance value for C(x) of 6 picofarads. A voltage level at E(gg) of 8.5 volts and at E(dd) of 5 volts; and an input voltage E(in) at either 0 or
8.5 volts. The circuit illustrated will give delays of 21 microseconds nominally for both up and down transitions, so that it is...