Browse Prior Art Database

Low Cost Integrated Timing

IP.com Disclosure Number: IPCOM000079405D
Original Publication Date: 1973-Jun-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Rocher, EY: AUTHOR

Abstract

A crystal clock source S of a signal of frequency fo supplies frequency comparator C with one input signal, which is compared to a second signal at a variable-output frequency f being fed back from an output line of a complementary metal-oxide semiconductor (CMOS) logic and integrated clock ring oscillator 0. The comparator provides a control voltage signal Vo tending to adjust frequency f to equal fo, by varying the frequency of oscillator 0. Oscillator 0 includes a ring of CMOS field-effect transistor (FET) inverters I(1),...I(9) which have bias inputs connected to a line connected to comparator C to receive signal Vo, which adjusts the bias inverters I to vary their rate of operation as a function of time. Fig. 2 shows details of inverter I(1).

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Low Cost Integrated Timing

A crystal clock source S of a signal of frequency fo supplies frequency comparator C with one input signal, which is compared to a second signal at a variable-output frequency f being fed back from an output line of a complementary metal-oxide semiconductor (CMOS) logic and integrated clock ring oscillator 0. The comparator provides a control voltage signal Vo tending to adjust frequency f to equal fo, by varying the frequency of oscillator 0. Oscillator 0 includes a ring of CMOS field-effect transistor (FET) inverters I(1),...I(9) which have bias inputs connected to a line connected to comparator C to receive signal Vo, which adjusts the bias inverters I to vary their rate of operation as a function of time. Fig. 2 shows details of inverter I(1).

The oscillator 0 includes an odd number of inverters 1, with the Output of the last one fed back into the input of the first inverter I. Attached to the outputs of the inverters I in several possible combinations are NAND or OR circuits G1 to G4, employed to produce square-wave signals having various time lengths. The output of any selected one of the inverters I(1), - I(9) or gates G1 to G4 can be fed back, as gate G is shown, as signal f to comparator C.

This circuit is desirable where the clock frequency is used in a slave station, or any full-duplex communication where the clock frequency has to be adjusted to the frequency of the incoming data stream, or where an external crystal clock is...