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Variable Delay Block for Josephson Tunneling Logic

IP.com Disclosure Number: IPCOM000079409D
Original Publication Date: 1973-Jun-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Herrell, DJ: AUTHOR

Abstract

To ensure correct operation in Josephson junction tunneling logic schemes employing terminated output lines, sufficient time delay must be introduced between logic gates.

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Variable Delay Block for Josephson Tunneling Logic

To ensure correct operation in Josephson junction tunneling logic schemes employing terminated output lines, sufficient time delay must be introduced between logic gates.

What is proposed is a combination of a modified OR gate (with a high- impedance output line) and a two input AND gate to provide a variable time-delay circuit. The output pulse of the modified OR gate is made slow rising, such that the time required to reach an amplitude sufficient to switch the AND gate represents the delay. The second input of the AND gate may be employed to adjust the switching point of the AND gate, by use of a variable bias.

The basic delay block consists of a typical terminated output line logic OR block (i.e., a gate having a threshold of + 1), with only one input; namely the data signal to be delayed [A]. This single input OR gate feeds a two input AND gate of the same terminated output line logic. The OR gate differs from a typical OR gate, in that the characteristic impedance of the output line [Z(1)] is relatively high and comparable (or equal) to the impedance of the supply lines [Z(s)]. The terminating resistor, R(t), however, is chosen to be low and, in general, equal to the terminating resistor value, R(t) = 2 Z(o).

When an input signal, A, is applied to the OR gate, the rise time of the current pulse flowing in the output line will rise relatively slowly with a time constant t(o), determined by the Z(1):R(t) rati...