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Automatic Heuristic Storage Paging Mechanism

IP.com Disclosure Number: IPCOM000079417D
Original Publication Date: 1973-Jun-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 49K

Publishing Venue

IBM

Related People

Davis, MI: AUTHOR

Abstract

A heuristically adaptive address translator controls storage management in a manner transparent to software, so that virtual storage operations are effected with minimal software overhead loading.

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Automatic Heuristic Storage Paging Mechanism

A heuristically adaptive address translator controls storage management in a manner transparent to software, so that virtual storage operations are effected with minimal software overhead loading.

In Fig. 1, processor 10 and channel 12 are isolated from main storage 14 and secondary backup storage 16 by address translator 15, which monitors those elements of data currently resident in 14 and fetches additional elements of data from high-volume backup storage 16 as demanded by 10 or 12. Data is also purged from 14 into 16 if not currently in use. Both 10 and 12 may address a range of storage 0 - X, whereas the capacity of 14 is less than X. By being transparent to software, the size of 14 can be increased to increase operating speed. Each word used in program execution can be considered divided into three blocks, the higher order bits representing a book number, the intermediary block of bits representing a page, and the lower order bits representing specific locations within the page. Pages are moved from 16 to 14, as required, and retained in 14 based upon activity.

Fig. 2 is an example of implementation where a program has loaded a 16-bit address into CPU storage address register 20. Low-order bits 8 - 15 directly address main storage 14. The address translator converts bits 0 - 7 to the high- order bits used for the address bus 21 to 14. The 0 - 7 bits are decoded to select one of 256 pages.

Fig. 3 shows a typical word contained in a location in the address translator, wherein address bit ADDR correspond to actual addresses within 14 for pages. K is set to 1 if write protection is desired, so that an attempt to write into a page will not be executed and a program check results. W flags whether or not the contents of the page have been changed while resident in 14. If so, purging of this page from 14 onto 16 must be accompanied by writing of the page in 14 into
16. If W is a 0, the contents of 16 are still accurate and a transfer is not necessary. A indicates activity and is set each time the page is accessed. It is reset by the circular passage of the purged pointer. F is a found flag wherein a particular page is located in main storage 14. If a 0, access to 16 is required. If F is a 1, the contents of ADDR are used as bits 0 - 7 at 21 in Fig. 2. P is the purged pointer which moves in a circular fashion from the top of the address translator array 22 to the bottom and returns to the top. As it moves, A bits through which it has passed that are set to a 1 are reset to 0. The function is to identify locations in 22 available when the next page must be fetched from 16. The array location in 22 designated by P will become the location loaded. The combination of P and A...