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Browse Prior Art Database

Bit Read/Write Control Circuit

IP.com Disclosure Number: IPCOM000079435D
Original Publication Date: 1973-Jul-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Chin, WB: AUTHOR

Abstract

The circuit described is a complementary metal-oxide semiconductor (CMOS) bit read/write (R/W) control circuit. It has particular utility in large-scale integrated memory applications.

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Bit Read/Write Control Circuit

The circuit described is a complementary metal-oxide semiconductor (CMOS) bit read/write (R/W) control circuit. It has particular utility in large-scale integrated memory applications.

In the drawing, transistors TN1 to TN8 are N-channel devices; transistors TP1 to TP8 are P-channel devices. The circuit is selected when the B.S. line is at V(H) (-V), thereby turning on devices TP7, TN2, TN5, TP2, and TP5.

For a read operation, the R/W control pulse goes to ground level, turning on devices TN4 and TP6. This allows the bit line signal B to be gated to the sense amplifier input S through devices TN6 and TP4. If the bit line is at V(H), node S will be discharged to ground through devices TP4, TP5 and TP6. If the bit line is at ground, node S will be charged to V(H) through devices TN4, TN5 and TN6. During the read cycle, the devices TN3 and TP1 are not conducting, preventing unwanted data from being gated on bit line B.

For a write operation, the R/W control pulse is at V(H) (-V), turning on devices TP8, TN3 and TP1. If the data is at V(H), bit line B will be discharged to ground through devices TP1, TP2 and TP3.

If the data is at ground, bit line B will charge to V(H) through device TN1, TN2 and TN3. During the write cycle, devices TN4 and TP6 are off, preventing unwanted data from being gated to the sense amplifier input.

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