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Variable Argument Logic Gate using Complementary Metal Oxide Semiconductors

IP.com Disclosure Number: IPCOM000079436D
Original Publication Date: 1973-Jul-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Lowden, RP: AUTHOR

Abstract

This is an OR-INVERT gate which accepts either a three or four-bit argument (input variables). It requires only a single stage of delay with no DC current power dissipation.

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Variable Argument Logic Gate using Complementary Metal Oxide Semiconductors

This is an OR-INVERT gate which accepts either a three or four-bit argument (input variables). It requires only a single stage of delay with no DC current power dissipation.

The circuit is illustrated in Fig. 1; and the truth table for the circuit is in Fig. 2. By selecting the proper code for inputs A and B, input 3 of the four-bit signal can be ignored. In the circuit of Fig. 1, this occurs when A = 1 and B = 0 as illustrated in the truth table. It is seen that the circuit operates as a standard OR-INVERT circuit for the remaining three inputs.

In operation, output C will be at +V (up) only when P-channel transistors P0, P1, P2 and P3 are on; this occurs when the inputs 0, 1, 2 and 3 are off. For all other combinations of inputs, at least one of the N-channel transistors: N0, N1, N2 or N3 is conductive and either NA or NB is conductive, thereby connecting C to ground (off).

Control line A and devices NA and PA are included for the case where the logic gate is disabled; by setting A = 0 and B = 0 the output C is forced to a 1, as shown in the truth table. If the disable function were not desired, control line A could be hand-wired to +V or devices NA and PA could be eliminated.

By reversing the P and N-channel devices, the gate becomes an AND INVERT logic gate.

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