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Browse Prior Art Database

Recessed Oxidation Method

IP.com Disclosure Number: IPCOM000079437D
Original Publication Date: 1973-Jul-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Klepner, SP: AUTHOR [+3]

Abstract

This process for producing recessed dielectric isolation avoids penetration of the oxide underneath the oxidation mask common to recessed oxidation techniques, where the mask consists of a silicon nitride over a silicon oxide layer.

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Recessed Oxidation Method

This process for producing recessed dielectric isolation avoids penetration of the oxide underneath the oxidation mask common to recessed oxidation techniques, where the mask consists of a silicon nitride over a silicon oxide layer.

In this process, subcollector region 10 and isolation diffusions 12 are made in wafer 14 in the conventional manner and an epitaxial layer 16 deposited thereon. Regions 10 and 12 diffuse upwardly into layer 16 as indicated. The oxidation mask 18 is then deposited directly on the surface of layer 16. The layer 18 is formed of silicon nitride and is deposited by sputtering in a conventional RF sputtering apparatus. It has been determined that the use of sputtered silicon nitride as an oxidation mask placed directly in contact with the silicon does not result in any adverse affects, such as dislocations.

As indicated in Fig. 2, openings 20, usually consisting of a grid configuration, are made in layer 18 using conventional etching techniques. The exposed silicon layer 16 in openings 20 has been etched to remove a portion thereof. Subsequently, as shown in Fig. 3, the device is exposed to an oxidizing atmosphere, which results in the formation of thick thermal regions 22 that extend down into the layer 16 to contact isolation diffused regions 12. Monocrystalline region 24 in layer 16 is thereby isolated at its sidewalls by regions 22 and at the bottom by a PN junction. Suitable active and/or passive devices can b...