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Complementary Metal Oxide Semiconductor Logic Testability

IP.com Disclosure Number: IPCOM000079438D
Original Publication Date: 1973-Jul-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Curtis, HW: AUTHOR

Abstract

In "stuck fault" testing of large-scale integration logic circuits, each pattern of inputs to a circuit should give a unique output. For complementary metal-oxide semiconductor circuits, certain faults (open gate or open drain in one of the parallel load devices) give an ambiguous output. This output will be either a "1" or "0", depending on the sequence of input patterns, rather than depending uniquely on the input pattern present at the time of measuring the output. The purpose of this technique is, through circuit means, to obviate calculation of sequences of inputs for each circuit and extended testing times for such sequences.

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Complementary Metal Oxide Semiconductor Logic Testability

In "stuck fault" testing of large-scale integration logic circuits, each pattern of inputs to a circuit should give a unique output. For complementary metal-oxide semiconductor circuits, certain faults (open gate or open drain in one of the parallel load devices) give an ambiguous output. This output will be either a "1" or "0", depending on the sequence of input patterns, rather than depending uniquely on the input pattern present at the time of measuring the output. The purpose of this technique is, through circuit means, to obviate calculation of sequences of inputs for each circuit and extended testing times for such sequences.

As an example, consider the two-input NAND circuit 8 in Fig. 1. If there are no defects in a circuit being tested, the following sequence of inputs gives outputs as shown: A B Output

0 0 1

0 1 1

1 0 1

1 1 0.

If there is an open circuit at point 10 in circuit 8, the same output sequence will result because of charge storage on the output line; this would give an indication that the faulty circuit was good.

The erroneous output can be avoided by use of circuit 12, together with appropriate lowering of the supply voltage between application of each test pattern. This use of the supply voltage bus to provide a leakage path to ground for all output nodes on a large-scale integration chip obviates wiring to separately activate the added discharge circuit. Power supply voltage during t...