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Program for Weighted Test Pattern Generation in Monte Carlo Testing of Integrated Circuits

IP.com Disclosure Number: IPCOM000079446D
Original Publication Date: 1973-Jul-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 5 page(s) / 107K

Publishing Venue

IBM

Related People

Schnurmann, HD: AUTHOR

Abstract

This description relates to random or Monte Carlo testing of integrated circuits. Such testing is generally described in U. S. Patents 3,614,608 and 3,633,100.

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Program for Weighted Test Pattern Generation in Monte Carlo Testing of Integrated Circuits

This description relates to random or Monte Carlo testing of integrated circuits. Such testing is generally described in U. S. Patents 3,614,608 and 3,633,100.

The advantages of weighting random-test pattern inputs has been recognized. U. S. Patent 3,719,885 describes apparatus in a test system for accomplishing such weighting. The publication entitled "Weighted Test Pattern Generation in Monte Carlo Testing of Integrated Circuits", published in the IBM Technical Disclosure Bulletin, Vol. 15, No. 6, November 1972, pages 1725 and 1726, describes in general a technique for accomplishing such weighting.

This article provides a description of a computer program for accomplishing such test pattern weighting.

With reference to the flow chart of Fig. 1, block 13 initializes an activity counter AC that keeps a record of how many gate outputs changed state from one binary level to the other, as the result of applying a pattern increment to the primary inputs of the circuit. Block 13 also initializes the matrix M by storing a 0 in all of its positions. The dimensions of M are such that its rows equal the number of pattern increments, and its columns, the number of components of the vector AC; that is, the number of primary inputs of the nonlinear integrated circuit. The purpose of M is to store the values that AC takes at the end of applying a pattern increment. It is also used as input to the subroutine PROCESS.

Block 14 interrogates whether the pattern increment is the first to be applied to the circuit. If the decision path is "NO", blocks 15, 16 and 17 are bypassed. These three blocks relate to how to update and handle the activity counter AC for each primary input. Since the first pattern increment assigns a binary value to usually more than one primary input, and often to all of them, it would be pointless to update the activity count, because several primary inputs may be the cause of the activity inside of the circuit. Consequently, no activity is recorded for the first pattern increment.

If the decision of the decision block 14 is "YES", block 15 counts AC1, the number of 1's stored in the appropriate slots of T0 and T1 as the result of applying the pattern increment to the circuit. Each pattern increment consists of a single primary input change. In block 16, the number AC1 is added to the previous total that has been accumulated, when previous pattern increments were applied to the circuit. Next, block 17 stores the new activity count of all the primary inputs in the row of M that corresponds to the number of the pattern increments that were applied. When the complete test pattern has been applied, all the rows of M are filled, the last row corresponding to the final activity count that each primary input has arrived at.

Next, block 18 calls the SUBROUTINE PROCESS, Figs. 2 and 2A, which determines what is the nature of the primary inputs.

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