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Testing of Random Logic

IP.com Disclosure Number: IPCOM000079450D
Original Publication Date: 1973-Jul-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Goel, P: AUTHOR [+2]

Abstract

This is a technique for testing random-sequential logic having inaccessible circuit nodes and requiring single input changes for testing.

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Testing of Random Logic

This is a technique for testing random-sequential logic having inaccessible circuit nodes and requiring single input changes for testing.

In a semiconductor integrated circuit chip, shift registers 12 and 14 are placed together with combinational logic circuits 16 and 18. For greater designed flexibility, it is desirable to place random logic 10 on the chip. Random logic 10 typically has a large number of inaccessible circuit nodes and contains sequential logic. In order to test this random logic 10, an additional independently shiftable shift register 20 is provided.

For testing random logic 10, test data is shifted into shift register 12 one bit at a time. When the desired pattern is reached in shift register 12, the desired test pattern is produced through the combinational logic 16 and applied in parallel into shift register 20 under the control of clock pulse C2. The output of random logic 10 is gated into shift register 14 by clock pulse C1. This result of the test may be shifted out of the chip for analysis and evaluation. Clock pulses C1 and control of clock pulse C2. The output of random logic 10 is gated into shift register 14 by clock pulse C1. This result of the test may be shifted out of the chip for analysis and evaluation. Clock pulses C1 and C2 are nonoverlapping.

An important aspect of the present technique is that during the shifting in of test patterns and shifting out of test results, gating of shifted clock pulses is c...