Browse Prior Art Database

Incremental Nodal Analysis for Chip Joining

IP.com Disclosure Number: IPCOM000079451D
Original Publication Date: 1973-Jul-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Gagnon, FL: AUTHOR [+2]

Abstract

This is a technique for testing the interconnection between a semiconductor chip and the substrate.

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This is the abbreviated version, containing approximately 84% of the total text.

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Incremental Nodal Analysis for Chip Joining

This is a technique for testing the interconnection between a semiconductor chip and the substrate.

In semiconductor integrated circuit technology, packaging density is improved by mounting a number of semiconductor circuit chips on a single substrate, such as a multilayer ceramic module. Each chip has a number of conductive connections, such as pads, for interconnecting the circuits on the semiconductor chip with the substrate. These interconnections must be tested to assure proper operation of the completed module.

By the present(technique, a current measurement is performed on each of the chip interconnection pads and the module I/O's after each chip is joined to the module substrate. To verify that a chip pad has been properly joined, it is only necessary to observe a current change at the node connected to the chip pad. It is not necessary to compare a measurement to a precalculated node characteristic after the entire net associated with the node has been formed. When a new chip is added to the module substrate, all nodes affected by that chip are measured and compared to the previous reading for the nodes. Any change must have been caused by the joining of the new chip. Any open circuits occasioned by the faulty interconnection of pads on the new chip, will cause no change to the node associated with that pad from the previous measurement.

To perform this type of test, it is necessary to keep the module at a temp...