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Increasing the Effective Speed of a Microprogram Store

IP.com Disclosure Number: IPCOM000079456D
Original Publication Date: 1973-Jul-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 57K

Publishing Venue

IBM

Related People

Faix, M: AUTHOR [+2]

Abstract

This method increases the effective speed of a microprogram store, without requiring changes in the memory organization or substantial additional hardware. All that is necessary is a change in the microinstruction specification.

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Increasing the Effective Speed of a Microprogram Store

This method increases the effective speed of a microprogram store, without requiring changes in the memory organization or substantial additional hardware. All that is necessary is a change in the microinstruction specification.

Taking as an example a microprogram section having the tree structure shown in Fig. 1, it will be seen that if each microinstruction contains a branch/no- branch (BR/BR) alternative, a microinstruction leads to at most two "next" instructions (A to BB', B to CC', etc.) and to at most four "after-next" instructions (A to CC'C''C''', B to DD'D''D''', etc.). The four "after-next" followers of a microinstruction are called "related alternatives". By arranging that related alternatives are stored in locations whose full addresses differ from one another in the two least significant bit positions only, any one of these addresses can be used as a "tetrad address" to specify up to four "after-next" instructions. The corresponding address is hereafter referred to as an "After-Next Instruction- Tetrad Address" (ANITA). By choosing the convention of inverting or not inverting the least significant address bit (instead of permanently assigning it to a "1" or a "0") for branch or no-branch, the microstore space can be utilized in full.

As is known, during the operation of monolithic memories, all bits of the "address input" to a chip must be valid before the "chip select" signal can be given, because the "address input" bits usually have to go through true/complement generators, decoders and drivers before they address a word line, whereas the "chip select" signal is used with considerably less time delay. Thus, if it is arranged that the "address input" bits are valid sufficiently long beforehand and that the "chip select" signal is derived at the latest possible instant from the least significant address bit, whose inversion has to await the branch/no-branch decision ensuing from the current microinstruction execution, then the various delays due to the resetting and setting of the microstore address register, the address decoding and the restoring of bit lines and sense amplifiers do not add to prolong the microinstruction cycle time. With this...