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Computer Performance Measurements

IP.com Disclosure Number: IPCOM000079465D
Original Publication Date: 1973-Jul-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 42K

Publishing Venue

IBM

Related People

Belady, LA: AUTHOR [+3]

Abstract

To allow monitoring, and recording measurements of the performance of a data-processing system with regard to specific operations and selected parts of a program in a flexible and efficient manner, a partly hardware partly software approach is taken.

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Computer Performance Measurements

To allow monitoring, and recording measurements of the performance of a data-processing system with regard to specific operations and selected parts of a program in a flexible and efficient manner, a partly hardware partly software approach is taken.

In addition to standard units of a data-processing system, of which main store 1, instruction register 2 and operation decode circuitry 3 are shown in the upper part of the drawing, the following are provided: a) counter 4 the contents of which can be initialized from, or can be stored into, main store 1; b) condition register 5, which can be loaded from main store 1 with a condition word comprising a condition mask of N bits and a condition key; c) comparator 6, for comparing a condition key contained in an instruction word with a condition key held in condition register 5; and d) logic circuitry including bistable device 7 for incrementing counter 4 between a start and a stop signal, when certain conditions are present.

Besides providing the above extra circuitry, five instructions are added to the standard instruction set of the data-processing system. These are: A) Initialize Counter (I); B) Store Counter (S); C) Load Condition Register (L); D) Start Counting; and E) Stop Counting. Instructions A, B and C comprise, besides the operation code, a main store address for the counter data, or condition data, respectively. Instructions D and E comprise, besides the operation code, a condition key which is to be compared to the condition key in condition register 5.

Gates 8, 9, 10 and 11 are provided for gating - depending on control signal I, S and L - an address from instruction register 2 to addressing circuitry of main store 1, and for gating data between the addressed storage location and counte...