Browse Prior Art Database

System Restart Facility

IP.com Disclosure Number: IPCOM000079475D
Original Publication Date: 1973-Jul-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Related People

Koman, TE: AUTHOR

Abstract

In a tightly coupled MP (multiprocessing) system where usage of control program resources is serialized by a hierarchical disabled lock-spinning mechanism, a system deadlock can occur if the highest locked resource is held by a CPU which is in an invalid disabled loop. Because of disablement, the system operator cannot break the deadlock, short of re-IPL (initial program load), which destroys the useful work being performed by the validly spinning CPU's. Even if the operator could interrupt the System externally, the selection of the CPU to interrupt, would be purely random and may be impossible to access physically.

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System Restart Facility

In a tightly coupled MP (multiprocessing) system where usage of control program resources is serialized by a hierarchical disabled lock-spinning mechanism, a system deadlock can occur if the highest locked resource is held by a CPU which is in an invalid disabled loop. Because of disablement, the system operator cannot break the deadlock, short of re-IPL (initial program load), which destroys the useful work being performed by the validly spinning CPU's. Even if the operator could interrupt the System externally, the selection of the CPU to interrupt, would be purely random and may be impossible to access physically.

The System Restart Facility is an operator-invoked hardware-supported software program in the control program of a tightly coupled MP system. This facility will break the system deadlock by releasing the locked resource held by an invalidly looping CPU, thus allowing the other spinning CPU's to continue normal operations.

The System Restart Facility may be dependent on the following hardware/software elements of the IBM System/370 MB machines and the VS/2-Release 2 control program. 1) The operation of the Console Restart key on the console of

the 370 MP CPU's. Specifically, the operation of storing the

current Program Status Word (PSW) at location 8 and loading

the PSW at location 0.

2) The operation of the SIGP (signal processor) instruction for

370 MP machines, which allows communication between the

various CPU's configured. Specifically, the "SIGP RESTART"

function which performs the identical operation as depressing

the console restart key on the CPU being SIGP'ed.

3) The existence of Functional Recovery Routines (FRR's) in the

control program defined per CPU, and associated with the

control program function currently spinning on the CPU. Each

such FRR when given control will provide the following return

information:

a. An indication whether this CPU is spinning validly or

invalidly.

b. If a valid spin, the CPU holding the resource for which the

FRR's CPU is spinning.

4) At system IPL, main storage location 0 is primed with the

address of the System Restart Facility so that when a Restart

is activated on any CPU, the system Restart Facility will get

control.

5) The Storage...