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Circuit Card Test Technique

IP.com Disclosure Number: IPCOM000079501D
Original Publication Date: 1973-Jul-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Casler, DH: AUTHOR [+2]

Abstract

Highly integrated data-processing machines can be composed of a set of distinct circuit card types, most of which may be used only once per machine. In such machines, the trouble-shooting technique of replacing or interchanging suspected cards is not feasible. Having a replacement set of cards on-site would be costly, while obtaining cards from a centralized inventory would be time consuming, particularly if the maintenance personnel must wait for a card only to find it is not the problem. If maintenance personnel could test the suspected cards on-site, however, only known faulty cards would need to be ordered from inventory. If the cards are operating correctly, attention can be immediately directed to search for other possible malfunctions.

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Circuit Card Test Technique

Highly integrated data-processing machines can be composed of a set of distinct circuit card types, most of which may be used only once per machine. In such machines, the trouble-shooting technique of replacing or interchanging suspected cards is not feasible. Having a replacement set of cards on-site would be costly, while obtaining cards from a centralized inventory would be time consuming, particularly if the maintenance personnel must wait for a card only to find it is not the problem. If maintenance personnel could test the suspected cards on-site, however, only known faulty cards would need to be ordered from inventory. If the cards are operating correctly, attention can be immediately directed to search for other possible malfunctions.

The arrangement shown involves a concept and a possible diagnostic hardware implementation scheme, to provide maintenance personnel with an on- site card test capability. Data from the CPU is loaded into the input buffer register 3 by a load and shift process under the control of the CPU interface controls 5. When full, the data is transferred to the test register 7, which is a polarity-hold device such that the outputs remain stable until altered by the input data. This is to ensure that no extraneous level changes occur during data loading. The outputs of the test register 7 are connected to all of the signal pins on a card test socket 9. These pins are also connected to a read register 11 which...