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Serialization Method for Display Logout and Scoping for High Density Logic Areas on Large Scale Integration Chips

IP.com Disclosure Number: IPCOM000079510D
Original Publication Date: 1973-Jul-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 3 page(s) / 62K

Publishing Venue

IBM

Related People

Howe, LD: AUTHOR [+2]

Abstract

With the higher density circuit packages now becoming available, the problem of displaying the large number of internal logic points contained within a field replaceable unit (FRU) 1 becomes more difficult. The larger number of circuits being packaged with a proportionally smaller number of input/output (I/O) pins, means that more logic points have to be displayed using fewer I/O pins. The method shown herein is a way of displaying a large amount of internal logic points (54 in this example) using only three I/O pins per FRU. These display points are generally the outputs of registers; but in this method they can be any internal logic node desired. The three pins required are a reset 5, an advance 4, and a serializer output pin 6.

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Serialization Method for Display Logout and Scoping for High Density Logic Areas on Large Scale Integration Chips

With the higher density circuit packages now becoming available, the problem of displaying the large number of internal logic points contained within a field replaceable unit (FRU) 1 becomes more difficult. The larger number of circuits being packaged with a proportionally smaller number of input/output (I/O) pins, means that more logic points have to be displayed using fewer I/O pins. The method shown herein is a way of displaying a large amount of internal logic points (54 in this example) using only three I/O pins per FRU. These display points are generally the outputs of registers; but in this method they can be any internal logic node desired. The three pins required are a reset 5, an advance 4, and a serializer output pin 6.

On each FRU there is a 6-bit serializer counter 2 and a 54-bit to 1-bit serializer 3. The reset line is used to reset counter 2 to a value of 0. The advance line couples microcode advance pulses to counter 2. Each time the advance line is raised and lowered, counter 2 advances its count by 1. Each of the first 54 values of the counter is used to gate a specific internal logic node into the serializer. The value of the selected node then appears on the serializer output pin of the FRU. This output pin will always contain the state of the selected node for the corresponding value of the counter.

The controls for the display mechanism is a 16-bit microcode controlled register called the display address register 7. The display address register contains: A reset (5 bits) - to reset all 6-bit counters 2 on all FRUs

and the shift ring counter 8 (to be explained later);

An advance (4 bits) - to advance all 6-bit counters 2 and the

shift ring counter 8; and 14-address bits - to tell the

display mechanism which display information is requested.

Other key parts of the display mechanism are:

The shift ring counter 8 - a counter that generates 6 values

(0-5), repeats these values (0-5, 0-5, 0-5) and is advanced

from the display address register advance bit;

An address decode 13 - that generates a starting value for the

shift ring counter 8, depending on the value of the address

in the display address register 7;

A shift register advance gate 12 - that generates an advance to

the deserializer shift r...