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Dynamic Logic Circuit

IP.com Disclosure Number: IPCOM000079520D
Original Publication Date: 1973-Jul-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Cole, TG: AUTHOR [+3]

Abstract

In high-density complex random-logic arrays, for example chips carrying a large number of dynamic logic gates, a problem arises because of signal coupling at data line crossovers. With conventional layout methods, circuit malfunction due to this problem is prevented by increasing the output padding capacitance at the gate output nodes, but this requires an increase in the size of the gate device to permit discharge of the output capacitance in the allowable phase time.

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Dynamic Logic Circuit

In high-density complex random-logic arrays, for example chips carrying a large number of dynamic logic gates, a problem arises because of signal coupling at data line crossovers. With conventional layout methods, circuit malfunction due to this problem is prevented by increasing the output padding capacitance at the gate output nodes, but this requires an increase in the size of the gate device to permit discharge of the output capacitance in the allowable phase time.

The figure shows an alternative gate layout which avoids this problem. In this arrangement, the input and output sequence of the gate are physically separate providing a node internal of the gate circuit, which node is distributed through the "noisy" crossover region rather than the output end as hitherto. The output precharge and strobe devices are on the receiving side of the crossovers, and the output end capacitance C does not require padding to swamp the crossover capacitances. A further advantage of the circuit is that the internal node X can be accessed, if desired, to provide a dot-OR.

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