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Array Logic Processing

IP.com Disclosure Number: IPCOM000079531D
Original Publication Date: 1973-Jul-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Elliott, JE: AUTHOR [+3]

Abstract

Sequential operations are enhanced for array logic by providing a selector circuit at the output to select grouped output signals, in accordance with desired functions to be performed. A plurality of inputs is supplied to the search or AND array via a usual input decode. Search results are supplied to a selection or read array, which selects which of the search results are to be supplied as possible output signals to the selector circuit.

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Array Logic Processing

Sequential operations are enhanced for array logic by providing a selector circuit at the output to select grouped output signals, in accordance with desired functions to be performed. A plurality of inputs is supplied to the search or AND array via a usual input decode. Search results are supplied to a selection or read array, which selects which of the search results are to be supplied as possible output signals to the selector circuit.

The read array has control portions for actuating the selector circuit via control signals traveling over lines 10, 11, and 12, for example. The regular output signals, which indicate results of data-processing functions from the search and read array, are supplied, respectively, over the illustrated cables to one or more of D-type latch registers 30, 31, and 32. The data lines are connected to the D inputs of such D-type latches. The control output signals from the read array are connected to AND circuits 20, 21, and 22. A clock signal times the control signals through the AND's to all C inputs in the D-type latch registers, respectively. By grouping the D-type latches, as shown, the AND's maximize read array efficiency and minimize the necessity for "maintain tables", by selectively degating unwanted outputs and storing results in the registers for more than one array cycle. Control signals on lines 10, 11, and 12 are generated in search array and read array, just as the normal outputs.

A typical application of the selector circuit is to provide a sequence of three functions without degating the search and read arrays, including the first function which provides result signals to register 30. Signals for registers 31 and 32, which are not pertinent to the functions being...