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Detecting Defective Circuit Cells in a Large Scale Integrated Masterslice

IP.com Disclosure Number: IPCOM000079543D
Original Publication Date: 1973-Jul-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Baker, TH: AUTHOR [+2]

Abstract

With the progress of large-scale integration, individual chips are becoming denser and denser in device capacity and, thus, relatively more expensive to replace. The present approach provides a method for determining defective circuit cells in a masterslice configuration, prior to the personalization of the masterslice. If the defective circuit cells are known, the chip may still be used if these cells are not interconnected into the final personalized circuit.

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Detecting Defective Circuit Cells in a Large Scale Integrated Masterslice

With the progress of large-scale integration, individual chips are becoming denser and denser in device capacity and, thus, relatively more expensive to replace. The present approach provides a method for determining defective circuit cells in a masterslice configuration, prior to the personalization of the masterslice. If the defective circuit cells are known, the chip may still be used if these cells are not interconnected into the final personalized circuit.

The method involves a preliminary and, preferably, temporary metallization layer applied to the chip interconnecting the circuit cells into a pyramid, as shown in the figure. With such a pyramid, a single output point is utilized and the required inputs are defined by the equation No. Cells = N(N+1) over 2 where N is the number of input points needed for a given number of cells. For example, in the structure shown in the figure, four inputs, I1 through I4, are needed to test ten circuit cells, C1 through C10.

With appropriate delay times assigned to each cell to conform with the circuit delay expected in the cell, AC testing may be carried out by applying a pulse to each input. Any defect in a given cell will interrupt the logic flow on a particular input point associated with the cell. Then, using standard pyramidal analysis techniques, the appropriate cell in which a defect occurs may be calculated, e.g., on a computer, by an elimi...