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Recessed Oxide Integrated Circuit Structure Utilizable for Mixed On and Off Chip Input

IP.com Disclosure Number: IPCOM000079545D
Original Publication Date: 1973-Jul-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Cass, EE: AUTHOR [+4]

Abstract

The present structure permits the simple combination of on and off-chip inputs in a single device. This is made possible by a recessed oxide arrangement employing four transistors all having a common collector, but wherein one of the transistors has its base and emitter isolated from the other three transistors by recessed oxide, while the remaining three transistors also have common bases. The arrangement permits the on and off-chip input to be combined in a single device, with a significant reduction in parasitic capacitance. In addition, higher packing density of devices is permitted.

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Recessed Oxide Integrated Circuit Structure Utilizable for Mixed On and Off Chip Input

The present structure permits the simple combination of on and off-chip inputs in a single device. This is made possible by a recessed oxide arrangement employing four transistors all having a common collector, but wherein one of the transistors has its base and emitter isolated from the other three transistors by recessed oxide, while the remaining three transistors also have common bases. The arrangement permits the on and off-chip input to be combined in a single device, with a significant reduction in parasitic capacitance.

In addition, higher packing density of devices is permitted.

In the illustrative example shown in the figures, Fig. 1 shows the circuit arrangement (T/2/L) described above. Base-collector junction of the transistor which is to receive the off-chip input is shorted by appropriate metallization.

Fig. 2 shows the planar layout of the structure, while Fig. 3 is a cross section of a typical transistor in the structure. The structure comprises a common collector region, N+, 10 with a collector contact diffusion 11 and a collector contact 12. This collector region is common to all of the transistors. Base region, P, 13 is common to the on-chip transistor, while base region 14 of the off- chip transistor is isolated from common base region 13 by recessed oxide region
15. All the transistors have N+ emitter regions 16.

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