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Floating Gate Field Effect Transistor Memory

IP.com Disclosure Number: IPCOM000079546D
Original Publication Date: 1973-Jul-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 88K

Publishing Venue

IBM

Related People

Chui, TL: AUTHOR [+3]

Abstract

This memory device utilizes the phenomena that the avalanching breakdown voltage of an N+ - P or P+ - N junction decreases, as the doping of the lighter doping side increases.

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Floating Gate Field Effect Transistor Memory

This memory device utilizes the phenomena that the avalanching breakdown voltage of an N+ - P or P+ - N junction decreases, as the doping of the lighter doping side increases.

In the device shown in Figs. 1 and 2, a floating polysilicon gate 10 is located over the region between the source 12 and drain region 14. As shown in the cross-sectional view of Fig. 2 taken on line 2-2 of Fig. 1, a P+ diffusion 16 is disposed in a shallower N diffusion 18 in the device that is spaced from 12 and
14. In addition, a metal erase gate 20 is provided which is separated from the polysilicon gate 10 by a layer of thermal oxide 22. An insulated metal avalanche injection electrode 24 makes contact with the diffusion 16.

In operation, information is stored in the device by introducing a charge into the floating polysilicon gate and erased by removing the charge, as is well known. In operation, electrons are introduced in the floating gate by avalanching injection, which is achieved by applying a negative voltage pulse slightly smaller than the breakdown voltage across the avalanching injection junction; that is, the PN junction between diffused regions 16 and 18 and the substrate. To remove the electrons from the floating gate, a positive voltage pulse is applied across the erase gate 20 and the substrate.

The memory device illustrated in Figs. 3 and 4 is a slightly modified version which operates on basically the same principle. Substra...