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Monolithically Integrated Flip Flop Control Circuit

IP.com Disclosure Number: IPCOM000079564D
Original Publication Date: 1973-Jul-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Berger, HH: AUTHOR [+2]

Abstract

To a flip-flop transistor a control circuit is connected, whose sensitivity is a function of the switching state of the flip-flop and which controls the flip-flop as a function of an input signal.

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Monolithically Integrated Flip Flop Control Circuit

To a flip-flop transistor a control circuit is connected, whose sensitivity is a function of the switching state of the flip-flop and which controls the flip-flop as a function of an input signal.

The monolithic layout of the control circuit including the flip-flop enables a high-integration density and minimum power dissipation, utilizing isolation-free merging of vertical and lateral transistor structures.

Fig. 1 shows a circuit diagram of the structure of Fig. 2. For example, the flip- flop used consists of two cross-coupled flip-flop transistors T1, T2 with two complementary load transistors T02, T01.

The control circuit comprises a control transistor T3 or T4 whose collector is connected to the base of associated flip-flop transistor T1 or T2, and whose base, via capacitor C1 or C2, is linked with an input E for the control signal.

Between the base of each flip-flop transistor T1 or T2 and the base of associated control transistor T3 or T4 coupling transistor T13 or T24 is formed.

For the indicated polarities the operation is as follows.

It is assumed that T1 is conductive and that the upper level (~0.7 V) of the control signal is applied to E. As the control signal is switched to the lower level (approx.) V), this negative voltage swing is transferred to the bases of T3 and T4, with T4 and T2 remaining blocked. As T1 is conductive, however, the secondary injection from its base (secondary emitter) to the b...