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Monolithically Integrated Logical Basic Circuit

IP.com Disclosure Number: IPCOM000079565D
Original Publication Date: 1973-Jul-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Berger, HH: AUTHOR [+2]

Abstract

The circuit consists of two complementary merged transistors, one of which is inversely operated. Since no isolations or resistors are necessary, optimal integration density is obtained.

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Monolithically Integrated Logical Basic Circuit

The circuit consists of two complementary merged transistors, one of which is inversely operated. Since no isolations or resistors are necessary, optimal integration density is obtained.

The collector-base path of transistor T1 is connected in parallel to the base- emitter path of inversely operated transistor T2. During operation, a current is impressed into emitter E1 of T1, which as a function of the input signal applied to its collector C1 and to base B2 of T2, respectively, controls the current flow through T2 (equivalent circuit diagram Fig. 1). This current serves as an output signal on collector C2.

In the monolithic realization csectional view Fig. 2) the two transistors are merged with each other in a vertical layer structure P1/N1/ P2/N2.

Collector zone P2+ of T1 is connected to base zone P2 of T2 and base zone N1 of T1 is connected to emitter zone N1 of T2. For contacting zones P2 and N1, zones P2+ and N1+ are provided.

The coupling of T1 and T2, as indicated, limits the design of the optimal layer thicknesses and the doping of the two transistors, so that an independent optimalization of the two transistors is made more difficult.

Due to the relatively deep zone P2+ extending into zone N1, it is ensured that emitter zone P1 injects mainly into that part of base zone N1 which has the smaller base width W1, rather than into the part having the greater width W2. Thus, the current amplification of T1 is pre...