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Data Detection and Thresholding Circuit

IP.com Disclosure Number: IPCOM000079571D
Original Publication Date: 1973-Jul-01
Included in the Prior Art Database: 2005-Feb-26
Document File: 2 page(s) / 13K

Publishing Venue

IBM

Related People

Keidl, SD: AUTHOR [+2]

Abstract

The data detection and thresholding circuit functions to detect valid data signals generated by a low-data rate magnetic read head, and exclude noise signals from being considered as valid data. The signals from the magnetic read head are positive and negative going pulses shouldered at zero potential. Thus, the detection circuit must detect both positive and negative going signals.

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Data Detection and Thresholding Circuit

The data detection and thresholding circuit functions to detect valid data signals generated by a low-data rate magnetic read head, and exclude noise signals from being considered as valid data. The signals from the magnetic read head are positive and negative going pulses shouldered at zero potential. Thus, the detection circuit must detect both positive and negative going signals.

The signals from the magnetic read head, not shown, are applied to input terminal 10, Fig. 1, which connects to amplifiers and filter stage 15. The output of 15, Shown as waveform A in Fig. 3, is applied to differentiator 30 and thresholding stage 60. Stages 15 and 30 detect the peaks of the input signal independent of its amplitude and its polarity, i.e., positive or negative going signals.

Details of stages 15 and 30 are shown in Fig. 2. Input noise is eliminated by a second-order Butterworth active filter.

Differentiator 30 converts the peaks of the amplified and filtered input signal to zero crossings, as represented by waveform B in Fig. 3. These zero crossings are detected by zero-crossing switch 40, Figs. 1 and 2, which generates square waves with each edge coincident with a zero crossing, as represented by waveform C in Fig. 3. This square-wave signal is then differentiated by square- wave differentiator 50 to provide trigger pulses with leading edges coincident with the input signal peaks, as represented by waveform D in Fig. 3. The output of differentiator 50 is applied to latch stage 90, but under control of thresholding stage 60.

Thresholding stage 60 either permits or prevents the output of differentiator 50 from switching latch stage 90, depending whether the signal from amplifier stage 15 exceeds or is below a predetermined threshold.

In Fig. 2 it is seen that threshold stage 60 includes differential comparators 65 and 70 and clamp transistor Q1. The DC bias condition at the + input of compar...